Responsibility:

Develop and maintain codec software for V-Silicon TV and STB solution
 

Qualifications
Required:

1. Bachelor’s degree or above in computer science, electronic engineering or related major
2. Interested in audio and video decoding and development
3. Familiar with C/C++                                                                
 
 

Primary Responsibilities:
 

 1. Responsible for porting and maintain  porting the Linux driver based on ARM architecture

 2. Responsible for the development and maintenance multimedia subsystem driver base on linux system

Primary Responsibilities:
 

1. Bachelor degree or above, major in computer science

2. Have IPC/ multimedia  software development experience, familiar with mainstream IPC/ multimedia development platform。

3. Proficient in C/C++ programming

4. Familiar with Linux Media Subsystem technology , V42L, ISP driver framework and hardware interface.

5.  Familiar with the camera modules’ framework, ISP related algorithm is preferred

6. Knowledge of  video codecs such as MPEG4,H.264,H. 265 and open source frameworks such as FFmpeg, GStreamer is preferred

7. Familiar with embedded system development tools, experience in GCC/GDB/ Eclipse is preferred.

8. Familiar with TCP/UDP/RTP/RTSP protocol development.

9. Hard working, good communication skills and team work spirit。

Primary Responsibilities:
 

1. Bachelor or master degree in computer science, electronics, physics or related field

2. At least 3 years related working experience
3. Familiar with image sensor technology

4. Familiar with color and image processing technology
5. Experience in image quality tunning of mobile phone, digital camera, ISP or related industry

6. Experience in auto exposure, auto white balance and auto focus algorithm development

7. Familiar with 3D noise reduction, WDR, HDR, color enhancement, Mosaic removal and other ISP Piplines

8. Proficient in using C++, Python and Matlab to develop image processing programs and tools

9. Experience in ISP driver development under Linux or Android is preferred

10. Good English listening, speaking, reading and writing skills, good communication skills, team work spirit, learning ability

1. AE, AF, AWB camera control algorithm development and improvement

2. ISP Debug tool development and improvement

3. ISP image quality tunning

4. Image quality test program customization and image quality evaluation

5. Responsible for bring-up of sensor
 

Primary Responsibilities:
 

1. Bachelor or master degree in computer science, electronics, physics or related field

2. At least 3 years related working experience

3. Familiar with image sensor technology

4. Familiar with color and image processing technology

5. Experience in image quality tunning of mobile phone, digital camera, ISP or related industry

6. Experience in auto exposure, auto white balance and auto focus algorithm development

7. Familiar with 3D noise reduction, WDR, HDR, color enhancement, Mosaic removal and other ISP Piplines

8. Proficient in using C++, Python and Matlab to develop image processing programs and tools

9. Experience in ISP driver development under Linux or Android is preferred

10. Good English listening, speaking, reading and writing skills, good communication skills, team work spirit, learning ability

Essential Job Functions: 

IC logic design (Front End) for Video Picture Quality Processing ICs or SOCs (System on Chip), including Verilog RTL coding, Simulation, Synthesis, Static Timing Analysis, Integration and Verification.

Experience:

1. Familiar with FE logic design flow, including RTL coding, simulation and verification, synthesis and static timing analysis

2. familiar with Linux/UNIX working environment, IC design EDA tools and C 

3. experience and knowledge of Video Picture Quality algorithm is a plus  

4. Good communication skill and team-work spirit?

Education: 

Major in EE or related fields. Master Degree or 2+ years of IC design experience

Essential Job Functions:

1. Takes definition, design, verification, and documentation for IP module level development. 2Determines infrastructure design, logic design.  

2. Integrates IP module into SOC full chip designs, and support simulation for SOCs. Contributes to the development of physical aware SOC designs considering the layout of complex integrated circuits. Performs all aspects of the SoC design flow from high-level design to synthesis, co-work with backend team for placing and routing, timing closure and power layout.

3. May also evaluate and review 3rd part IP’s capability for further process.  

4. Co-work with and support other SoC design engineers to ensure the efficient operation of the function.  

5. Co-work with software engineers, hardware engineers to complete the chip system testing and debugging.

Experience:
 

Experience with peripheral IP design such as USB/SDIO/FLASH/EHERNET/UART/SPI etc. is preferred.

Education:

 BS or MS in Electrical, computer or related fields with at least 5 years of relevant experience

Primary Responsibilities:

 1. Proficient in IC digital design process and related EDA tools
 2. Proficient in Verilog/VHDL and other hardware description languages, with rich experience in RTL level code writing 
 3. Proficient in AHB/AXI/ACE/CHI bus protocols, familiar with Cache consistency protocols (MESI/MOESI...)
 4. Familiar with DDR3/LPDDR3/DDR4/LPDDR4 protocols
 5. Good command of SystemVerilog language, familiar with UVM validation environment is preferred
 6. Strong analytical thinking and problem solving skills with great attention to detail
 7. Organized, self-motivated and able to work effectively across internal and multiple teams
 8. Ability to prioritize multiple tasks and drive them to completion

 1. Responsible for SoC chip project system, interface and other aspects of digital circuit design and project delivery

 2. Responsible for module specification, RTL code writing, design report and validation support

 3. Responsible for the compilation of Constraint file for module synthesis and sequence analysis

 4. Responsible for upF documentation of low power design

 5. Responsible for chip module function debugging and application support

Primary Responsibilities:
 
 1. At least 5 years of ASIC/FPGA microarchitecture, design or validation experience

 2. At least 3 years experience in front-end complex RTL Verilog design
 3. Proficient in IC digital design process and related EDA tools
 4. Good command of SystemVerilog language, familiar with UVM validation environment is preferred
 5. Experience in SOC integration, CPU, DDR or other interface module design is preferred
 6. Strong analytical thinking and problem solving skills with great attention to detail
 7. Good communication skill, team work spirit, learning ability

Primary Responsibilities:

1. Master degree or above in microelectronics, computer, communication or related field
2. Familiar with IC digital design process and related EDA tools
3. Proficient in Verilog/VHDL and other hardware description languages, with rich experience in RTL level code writing
4. Good command of SystemVerilog language, familiar with UVM validation environment is preferred